As the use of elastic cloud architectures and mobile computing systems increases, the need for an additional layer of software based networking arises. The research community has proposed open standards to specify network services without coupling specifications with network interfaces, referred to as Software Defined Networking (SDN). Such a software layer can improve the performance of network routers and switches. As demands due to network security increase, aggregation of traffic from diverse applications including high performance computing will further require novel solutions for the data plane.



This project explores hardware as well as software-based solutions to optimize the SDN data plane with respect to latency, throughput, and power efficiency. The work investigates novel algorithms, data structures, and architectures that exploit state-of-the-art technologies including heterogeneous multi-processor system-on-chip architectures, multi/many-core processors, and Programmable Gate Arrays to realize flexible designs for data plane kernels and understand performance tradeoffs. Novel solutions based on hashing and data structures for large-scale IP lookup as well as parallel solutions for multi-field packet classification to support high performance will be developed. The work also develops new techniques for network virtualization and data aggregation using hybrid trees and virtual engines to achieve high performance on various platforms. The broader impact of the project includes providing a flexible and scalable solution for a high performance Internet backbone to support next generation networking.



  • Publications
    1. Shijie Zhou, Yun R. Qu, and Viktor K. Prasanna, [Large-scale Packet Classification on FPGA, IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), July 2015
    2. Yun R. Qu, Hao H. Zhang, Shijie Zhou and Vikor K. Prasanna, Optimizing Many-field Packet Classification on FPGA, multi-core General Purpose Processor, and GPU, ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS), 2015.
    3. Yun R. Qu, Viktor Prasanna, High-performance and Dynamically Updatable Packet Classification Engine on FPGA, IEEE Transactions on Parallel and Distributed Systems (TPDS), 2014.
    4. Yun R. Qu, Shijie Zhou and Viktor Prasanna, High-performance Architecture for Dynamically Updatable Packet Classification on FPGA, ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS), 2013.
    5. Da Tong, Lu Sun, Kiran Matam and Viktor Prasanna, High throughput and programmable online traffic classifier on FPGA, ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA), 2013.